What Goes In Register Banks

Section 2.7: 8051 Register BANKS AND STACK

The 8051 microcontroller has a full of 128 bytes of RAM. In this department nosotros discuss the allocation of these 128 bytes of RAM and examine their usage as registers and stack.

RAM retentivity infinite resource allotment in the 8051

There are 128 bytes of RAM in the 8051 (some members, notably the 8052, have 256 bytes of RAM). The 128 bytes of RAM inside the 8051 are assigned addresses 00 to 7FH. As we will see in Chapter 5, they can be accessed straight every bit memory locations. These 128 bytes are divided into three different groups equally follows.

Figure 2-5. RAM Allocation in the 8051

A total of 32 bytes from locations
00 to IF hex are set aside for reg
ister banks and the stack.
A full of xvi bytes from locations
20H to 2FH are ready aside for chip-
addressable read/write memory. A
detailed discussion of scrap-address
able memory and instructions is
given in Affiliate 8.
A total of 80 bytes from locations
30H to 7FH are used for read and
write storage, or what is normally
called a scratch pad. These 80
locations of RAM are widely used
for the purpose of storing data and
parameters by 8051 programmers.
We will apply them in future chap
ters to store data brought into the
CPU via I/O ports. 1

Annals banks in the 8051

As mentioned earlier, a total of 32 bytes of RAM are set aside for the register banks and stack. These 32 bytes are divided into iv banks of registers in which

each bank has eight registers, RO – R7. RAM locations from 0 to seven are ready aside for banking company 0 of RO – R7 where RO is RAM location 0, Rl is RAM location 1, R2 is location 2, so on, until retention location vii, which belongs to R7 of banking concern 0. The second banking company of registers RO – R7 starts at RAM location 08 and goes to location OFH. The 3rd banking concern of RO – R7 starts at memory location 10H and goes to location 17H. Finally, RAM locations 18H to 1FH are set aside for the fourth bank of RO – R7. The post-obit shows how the 32 bytes are allocated into iv banks:

Figure 2-6. 8051 Register Banks and their RAM Addresses

As we can come across from Effigy 2-5, bank one uses the same RAM space as the stack. This is a major trouble in programming the 8051. Nosotros must either non use register bank 1, or classify another area of RAM for the stack. This will be discussed below.

Default register depository financial institution

If RAM locations 00 – 1F are set up bated for the iv annals banks, which •register bank of RO – R7 practise we have access to when the 8051 is powered upward? The answer is annals bank 0; that is, RAM locations 0, i,2, 3, four, 5, vi, and vii are accessed with the names RO, Rl, R2, R3, R4, R5, R6, and R7 when programming the 8051. It is much easier to refer to these RAM locations with names such as RO, R1, and so on, than by their retentiveness locations. Example 2-half-dozen clarifies this concept.

How to switch register banks

As stated above, register bank 0 is the default when the 8051 is powered up. We can switch to other banks by use of the PSW (program status discussion) annals. Bits D4 and D3 of the PSW are used to select the desired register depository financial institution as

shown in Table 2-2.

The D3 and D4 bits of register PSW are often referred to as PSW.4 and PSW.three since they tin be accessed past the fleck-addressable instructions SETB and CLR. For example, "SETB PSW.3″ will brand PSW.3 = 1 and select bank annals i. See Instance ii-7.

Stack in the 8051

The stack is a section of RAM used by the CPU to store information temporarily. This information could be data or an address. The CPU needs this storage surface area since there are but a express number of registers.

How stacks are accessed in the 8051

If the stack is a section of RAM, there must be registers inside the CPU to point to it. The annals used to admission the stack is chosen the SP (stack arrow) register. The stack arrow in the 8051 is merely viii bits broad, which ways that it tin can take values of 00 to FFH. When the 8051 is powered up, the SP register contains value 07. This means that RAM location 08 is the get-go location used for the stack by the 8051. The storing of a CPU annals in the stack is called a Push, and pulling the contents off the stack dorsum into a CPU register is called a POP. In other words, a register is pushed onto the stack to salvage information technology and popped off the stack to recollect it. The task of the SP is very critical when push and pop deportment are performed. To encounter how the stack works, permit's look at the PUSH and POP instructions.

Pushing onto the stack

In the 8051 the stack arrow (SP) points to the last used location of the stack. Equally we button data onto the stack, the stack pointer (SP) is incremented past one. Notice that this is unlike from many microprocessors, notably x86 processors in which the SP is decremented when data is pushed onto the stack. Examining Example 2-8, we see that equally each PUSH is executed, the contents of the register are saved on the stack and SP is incremented by 1. Discover that for every byte of information saved on the stack, SP is incremented just once. Notice besides that to push the registers onto the stack we must apply their RAM addresses. For case, the instruction "PUSH i″ pushes register Rl onto the stack.

Popping from the stack

Popping the contents of the stack back into a given register is the opposite process of pushing. With every pop, the top byte of the stack is copied to the annals specified past the instruction and the stack pointer is decremented once. Instance 2-nine demonstrates the POP education.

The upper limit of the stack

As mentioned earlier, locations 08 to IF in the 8051 RAM tin be used for the stack. This is considering locations xx – 2FH of RAM are reserved for bit-addressable retentivity and must not be used past the stack. If in a given program nosotros need more than than 24 bytes (08 to 1FH = 24 bytes) of stack, we can change the SP to point to RAM locations thirty – 7FH. This is washed with the education "MOV SP, #xx".

CALL instruction and the stack

In addition to using the stack to save registers, the CPU likewise uses the stack to save the address of the instruction just below the CALL educational activity. This is how the CPU knows where to resume when information technology returns from the called subroutine. More than data on this will be given in Chapter three when we discuss the CALL instruction.

Stack and banking company 1 conflict

Think from our earlier discussion that the stack arrow register points to the current RAM location available for the stack. As data is pushed onto the stack, SP is incremented. Conversely, it is decremented as data is popped off the stack into the registers. The reason that the SP is incremented after the push is to make sure that the stack is growing toward RAM location 7FH, from lower addresses to upper addresses. If the stack arrow were decremented subsequently push instructions, we would be using RAM locations 7, 6, 5, etc., which belong to R7 to RO of bank 0, the default register depository financial institution. This incrementing of the stack pointer for push instructions also ensures that the stack will not reach location 0 at the bottom of RAM, and consequently run out of infinite for the stack. Yet, at that place is .a problem with the default setting of the stack. Since SP = 07 when the 8051 is powered upwardly, the first location of the stack is RAM location 08, which also belongs to annals RO of register depository financial institution 1. In other words, register banking company i and the stack are using the same retentiveness space. If in a given plan nosotros need to apply register banks ane and 2, we tin reallocate another section of RAM to the stack. For example, we tin allocate RAM locations 60H and higher to the stack as shown in Instance 2-10.

Viewing registers and memory with a simulator

Many assemblers and C compilers come with a simulator. Simulators allow us to view the contents of registers and retentiveness after executing each instruction (single-stepping). We strongly recommend that you employ a simulator to single-step some of the programs in this chapter and time to come chapters. Single-stepping a program with a simulator gives us a deeper agreement of microcontroller architecture, in addition to the fact that we tin use information technology to find errors in our programs. Figures ii-

Figure two-7. Register'due south Screen from Pro View 32 Simulator

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Figure ii-8.128-Byte Memory Infinite from Pro View 32 Simulator

Effigy two-9. Register's Screen from Keil Simulator

Figure 2-10.128-Byte Memory Space from Keil Simulator

SUMMARY

This chapter began with an exploration of the major registers of the 8051, including A, B, RO, Rl, R2, R3, R4, R5, R6, R7, DPTR, and PC. The use of these registers was demonstrated in the context of programming examples. The process of creating an Assembly language program was described from writing the source file, to assembling it, linking, and executing the programme. The PC (plan counter) register always points to the side by side education to exist executed. The way the 8051 uses program ROM space was explored because 8051 Assembly language programmers must exist aware of where programs are placed in ROM, and how much memory is available.

An Assembly language program is composed of a serial of statements that are either instructions or pseudo-instructions, also called directives. Instructions are translated by the assembler into auto code. Pseudo-instructions are not translated into machine code: They directly the assembler in how to translate instructions into car code. Some pseudo-instructions, called data directives, are used to define data. Information is allocated in byte-size increments. The data can be in binary, hex, decimal, or ASCII formats.

Flags are useful to programmers since they indicate certain conditions, such as bear or overflow, that result from execution of instructions. The stack is used to shop data temporarily during execution of a program. The stack resides in the RAM space of the 8051, which was diagrammed and explained. Manipulation of the stack via Popular and Push button instructions was also explored.